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Advanced Computer Architecture-CS501
Advanced Computer Architecture
Lecture No. 32
Reading Material
Vincent P. Heuring & Harry F. Jordan
Chapter 9
Computer Systems Design and Architecture
Hard Disk
Static and Dynamic Properties
Mechanical Delays and Flash Memory
Semiconductor Memory vs. Hard Disk
Hard Disk
Peripheral devices connect the outside world with the central processing unit through the
I/O modules. One important feature of these peripheral devices is the variable data rate.
Peripheral devices are important because of the function they perform.
A hard disk is the most frequently used peripheral device. It consists of a set of platters.
Each platter is divided into tracks. The track is subdivided into sectors. To identify each
sector, we need to have an address. So, before the actual data, there is a header and this
header consisting of few bytes like 10 bytes. Along with header there is a trailer. Every
sector has three parts: a header, data section and a trailer.
Static Properties
The storage capacity can be determined from the number of platters and the number of
tracks. In order to keep the density same for the entire surface, the trend is to use more
number of sectors for outer tracks and lesser number of sectors for inner tracks.
Dynamic Properties
When it is required to read data from a particular location of the disk, the head moves
towards the selected track and this process is called seek. The disk is constantly rotating
at a fixed speed. After a short time, the selected sector moved under the head. This
interval is called the rotational delay. On the average, the data may be available after half
a revolution. Therefore, the rotational latency is half revolution.
The time required to seek a particular track is defined by the manufacturer. Maximum,
minimum and average seek times are specified. Seek time depends upon the present
position of the head and the position of the required sector. For the sake of calculations,
we will use the average value of the seek time.
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 Transfer rate
When a particular sector is found, the data is transferred to an I/O module. This would
depend on the transfer rate. It would typically be between 30 and 60 Mbytes/sec defined
by the manufacturer.
 Overhead time
Up till now, we have assumed that when a request is made by the CPU to read data, then
hard disk is available. But this may not be the case. In such situation we have to face a
queuing delay. There is also another important factor: the hard disk controller, which is
the electronics present in the form of a printed circuit board on the hard disk. So the time
taken by this controller is called over head time.
The following examples will clarify some of these concepts.
Example 1
Find the average rotational latency if the disk rotates at 20,000 rpm.
The average latency to the desired data is halfway round the disk so
Average rotational latency =0.5/(20,000/60)
Example 2
A magnetic disk has an average seek time of 5 ms. The transfer rate
is 50 MB/sec. The disk rotates at 10,000 rpm and the controller overhead is 0.2 msec.
Find the average time to read or write 1024 bytes.
Average Tseek=5ms
Average Trot=0.5*60/10,000=3 ms
The total time taken= Tseek +Trot+ Ttsfr +Tctr
=8.22 ms
Example 3
A hard disk with 5 platters has 1024 tracks per platter,512 sectors
per track and 512 bytes/sector. What is the total capacity of the
512 bytes x 512
0.2MB x 1024 tracks=0.2GB/platter
Therefore the hard disk has the total capacity of 5 x 0.2=1GB
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Example 4
How many platters are required for a 40GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter
The capacity of one platter
= 1024 x 2048 x 4096
= 8GB
For a 40GB hard disk, we need 40/8
= 5 such platters.
Example 5
Consider a hard disk that rotates at 3000 rpm. The seek time to move
the head between adjacent tracks is 1 ms. There are 64sectors per
track stored in linear order.
Assume that the read/write head is initially at the start of sector 1 on track 7.
a. How long will it take to transfer sector 1 on track 7 to sector 1 on track 9?
b. How long will it take to transfer all the sectors on track 12 to corresponding
sectors on track 13?
Time for one revolution=60/3000=20ms
Total transfer time=sector read time+head
movement time+rotational delay+sector write time
Time to read or write on sector=20/64=0.31ms/sector
Head movement time from track 7 to track 9=1msx2=2ms
After reading sector 1 on track 7, which takes .31ms, an  additional 19.7 ms of
rotational delay is needed for the head to line up with sector 1 again.
The head movement time of 2 ms gets included in the19.7 ms.
transfer time=0.31ms+19.7ms+0.31ms=20.3ms
b. The time to transfer all the sectors of track 12 to track 13 can be computed in the
similar way. Assume that the memory buffer can hold an entire track. So the time
to read or write an entire track is simply the rotational delay for a track, which is
20 ms. The head movement time is 1ms, which is also the time for 1/0.3=3.34
sectors to pass under the head. Thus after reading a track and repositioning the
head, it is now on track 13, at four sectors past the initial sector that was read on
track 12. (Assuming track 13 is written starting at sector 5)
therefore total transfer time= 20+1+20=41ms.
If writing of track 13 start at the first sector, an additional 19 ms  should be
added, giving a total transfer time= 60 ms
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Example 6
Calculate time to read 64 KB (128 sectors) for the following disk parameters.
­180 GB, 3.5 inch disk
­12 platters, 24 surfaces
­7,200 RPM; (4 ms avg. latency)
­6 ms avg. seek (r/w)
­64 to 35 MB/s (internal)
­0.1 ms controller time
Disk latency = average seek time + average rotational delay + transfer
time +
controller overhead
= 6 ms + 0.5 x 1/(7200 RPM) /(60000ms/M)) + 64 KB / (64 MB/s) + 0.1 ms
= 6 + 4.2 + 1.0 + 0.1 ms = 11.3 ms
Mechanical Delay and Flash Memory
Mechanical movement is involved in data transfer and causes mechanical delays which
are not desirable in embedded systems. To overcome this problem in embedded systems,
flash memory is used. Flash memory can be thought of a type of electrically erasable
PROM. Each cell consists of two MOSFET and in between these two transistors, we have
a control gate and the presence/absence of charge tells us that it is a zero or one in that
location of memory.
The basic idea is to reduce the control overheads, and for a FLASH chip, this control
overhead is low. Furthermore flash memory has low power dissipation. For embedded
devices, flash is a better choice as compared to hard disk. Another important feature is
that read time is small for flash. However the write time may be significant. The reason is
that we first have to erase the memory and then write it. However in embedded system,
number of write operations is less so flash is still a good choice.
Example 7
Calculate the time to read 64 KB for the previous disk, this time using 1/3 of quoted seek
time, 3/4 of internal outer track bandwidth
Disk latency = average seek time + average rotational delay + transfer time + controller
= (0.33* 6 ms) + 0.5 * 1/(7200 RPM)
+ 64 KB / (0.75* 64 MB/s) + 0.1 ms
= 2 ms + 0.5 /(7200 RPM/(60000ms/M))
+ 64 KB / (48 KB/ms) + 0.1 ms
= 2 + 4.2 + 1.3+ 0.1 ms = 7.6 ms
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Semiconductor Memory vs. Hard Disk
At one time developers thought that development of semiconductor memory would
completely wipe out the hard disk. There are two important features that need to be kept
in mind in this regard:
1. Cost
It is low for hard disk as compared to semi-conductor memory.
2. Latency
Typically latency of a hard disk is in milliseconds. For SRAM, it is 105 times lower as
compared to hard disk.
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Table of Contents:
  1. Computer Architecture, Organization and Design
  2. Foundations of Computer Architecture, RISC and CISC
  3. Measures of Performance SRC Features and Instruction Formats
  4. ISA, Instruction Formats, Coding and Hand Assembly
  5. Reverse Assembly, SRC in the form of RTL
  6. RTL to Describe the SRC, Register Transfer using Digital Logic Circuits
  7. Thinking Process for ISA Design
  8. Introduction to the ISA of the FALCON-A and Examples
  9. Behavioral Register Transfer Language for FALCON-A, The EAGLE
  10. The FALCON-E, Instruction Set Architecture Comparison
  11. CISC microprocessor:The Motorola MC68000, RISC Architecture:The SPARC
  12. Design Process, Uni-Bus implementation for the SRC, Structural RTL for the SRC instructions
  13. Structural RTL Description of the SRC and FALCON-A
  14. External FALCON-A CPU Interface
  15. Logic Design for the Uni-bus SRC, Control Signals Generation in SRC
  16. Control Unit, 2-Bus Implementation of the SRC Data Path
  17. 3-bus implementation for the SRC, Machine Exceptions, Reset
  18. SRC Exception Processing Mechanism, Pipelining, Pipeline Design
  19. Adapting SRC instructions for Pipelined, Control Signals
  20. SRC, RTL, Data Dependence Distance, Forwarding, Compiler Solution to Hazards
  21. Data Forwarding Hardware, Superscalar, VLIW Architecture
  22. Microprogramming, General Microcoded Controller, Horizontal and Vertical Schemes
  23. I/O Subsystems, Components, Memory Mapped vs Isolated, Serial and Parallel Transfers
  24. Designing Parallel Input Output Ports, SAD, NUXI, Address Decoder , Delay Interval
  25. Designing a Parallel Input Port, Memory Mapped Input Output Ports, wrap around, Data Bus Multiplexing
  26. Programmed Input Output for FALCON-A and SRC
  27. Programmed Input Output Driver for SRC, Input Output
  28. Comparison of Interrupt driven Input Output and Polling
  29. Preparing source files for FALSIM, FALCON-A assembly language techniques
  30. Nested Interrupts, Interrupt Mask, DMA
  31. Direct Memory Access - DMA
  32. Semiconductor Memory vs Hard Disk, Mechanical Delays and Flash Memory
  33. Hard Drive Technologies
  34. Arithmetic Logic Shift Unit - ALSU, Radix Conversion, Fixed Point Numbers
  35. Overflow, Implementations of the adder, Unsigned and Signed Multiplication
  36. NxN Crossbar Design for Barrel Rotator, IEEE Floating-Point, Addition, Subtraction, Multiplication, Division
  37. CPU to Memory Interface, Static RAM, One two Dimensional Memory Cells, Matrix and Tree Decoders
  38. Memory Modules, Read Only Memory, ROM, Cache
  39. Cache Organization and Functions, Cache Controller Logic, Cache Strategies
  40. Virtual Memory Organization
  41. DRAM, Pipelining, Pre-charging and Parallelism, Hit Rate and Miss Rate, Access Time, Cache
  42. Performance of I/O Subsystems, Server Utilization, Asynchronous I/O and operating system
  43. Difference between distributed computing and computer networks
  44. Physical Media, Shared Medium, Switched Medium, Network Topologies, Seven-layer OSI Model