

Advanced Computer
ArchitectureCS501
________________________________________________________
Advanced
Computer Architecture
Lecture
No. 36
Reading
Material
Vincent
P. Heuring & Harry F. Jordan
Chapter
6
Computer
Systems Design and Architecture
6.3.2,
6.4, 6.4.1
6.4.2,
6.4.3
Summary
·
NxN
Crossbar Design for Barrel
Rotator
·
Barrel
Shifter with Logarithmic
Number of Stages
·
ALU
Design
·
FloatingPoint
Representations
·
IEEE
FloatingPoint Standard
·
FloatingPoint
Addition and Subtraction
·
FloatingPoint
Multiplication
·
FloatingPoint
Division
NxN
Crossbar Design for Barrel
Rotator
Figure
6.11 of the text
book
The
figure shows an NxN crossbar design
for barrel rotator. x
indicates the input.
So
x0,x1,...,xn1
are applied to the rows.
The vertical lines are
indicated by y1,
y2,...yn1
where y
shows the output. So this
forms a cross of x and y and the
number of cross
points
are NxN.
There is also a connection between
each input and output using
a tristate
buffer.
At the input, we have a
decoder which is used to select
the shift count. Each
output
from the decoder is
connected diagonally to the
tristate buffers. This
arrangement
requires
N2 gates.
Barrel
Shifter with Logarithmic Number of
Stages
Another
alternate to an NxN crossbar barrel
rotator is a logarithmic barrel
shifter. This
design is timespace
tradeoff. In this case, the
number of shifts required is
eight, and
then
there will be three stages
for this purpose. Now a word
is passed as input to
the
shifter.
There are two possibilities.
First the input word is
passed to the next stage
without
any
shift. This process is
called bypass and second
option is shift. The word is
passed to
the
next stage after
shift.
For
the first stage, we have
1bit right shift, for
second stage, 2bit right
shift and so on.
There is
also a shift count unit
which controls the number of
shifts. For example, if
1bit
shift is
required then only s0 will be one and
other signals from shift
count will be zero. If
we want a
3bit shift, then s0 and s1 will be 1 and
all other signals will be
zero.
The
figure also shows one shift/bypass
cell which is a combinational
logic circuit. A
shift/bypass
signal decides whether the
input word should be shifted
or bypassed. This
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Advanced Computer
ArchitectureCS501
________________________________________________________
design
requires only O (NlogN)
switches but propagation
delay has increased i.e.
from
O(1) to
O(logN).
Figure
6.12 of the text
book
ALU
Design
ALU is a
combination of arithmetic, logic and
shifter unit along with
some multiplexers
and
control unit. The idea is
that based on the opcode of an
instruction, appropriate
control
signals are activated to
perform required ALU
operation.
Figure
6.13 of the text
book
The
diagram shows two inputs x
and y and one output z. All these are of
nbits. The
inputs x
and y are simultaneously provided to
arithmetic, logic and shifter
unit. There is a
control
unit which accepts opcode as
input. Based on the opcode, it
provides control
signals
to arithmetic, logic and shifter
unit. The control unit also
provides control
signals
to the
two multiplexers. One mux
has three inputs; each
from arithmetic, logic and
shifter
unit and
its output is z. The second
mux provides status output
corresponding to
condition
codes.
Floating Point
Representations
Example
0.5 ×
103
Sign =
1
Significand=
0.5
Exponent=
3
Base =
10= fixed for given
type of representation
Significand
is also called mantissa.
In
computers, floatingpoint representation
uses binary numbers to
encode significant,
exponent
and their sign in a single
word.
The
diagram on Page 293 of the
text shows an mbit floating
point number where s
represents
the sign of the floating
point number. If s = 1 then
the floatingpoint
number
will be a
positive number; if s= 0 then it will be
a negative number. The e
field shows the
value of
exponent. To represent the exponent, a
biased representation is used. So
we
represent e^ instead
of e to show biased representation. In
this technique, a number
is
added to
the exponent so that the
result is always positive. In
general floating
point
numbers
are of the form.
(1)s × f
× 2e
Normalization
A
normalized, non zero
floating point number has a
significand whose leftmost
digit is
non
zero and is a single
number.
Example
0.56 ×
103........... (Not normalized)
5.6 ×
103........... (Normalized form)
Same is
the case for
binary.
IEEE
FloatingPoint Standard
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Advanced Computer
ArchitectureCS501
________________________________________________________
IEEE
floating point standard has
the following
features.
SinglePrecision
Binary Floating Point
Representation
· 1bit
sign
· 8bit
exponent
· 23bit
fraction
· A
bias of 127 is used.
Figure
6.15 of the text
book
Double
precision Binary Floating
Point Representation
· 1bit
sign
· 11bit
exponent
· 52bit
fraction
· Exponent
bias is 1023
Figure
6.16 of the text
book.
Overflow
In table
6.7 of the text book,
e^= 255, denotes numbers
with no numeric value
including
+ ∞ and  ∞ and
called NotaNumber or NaN. In
computers, a floatingpoint
number
ranges
from 1.2 × 1038 ≤ x ≤ 3.4 ×
1038 can be represented. If a number does
not lie in
this
range, then overflow can
occur.
Overflow
occurs when the exponent is
too large and can not be
represented in the
exponent
field.
Floating
Point Addition and
Subtraction
The
following are the steps
for floatingpoint addition and
subtraction.
· Unpack
sign , exponent and fraction
fields
· Shift
the significand
· Perform
addition
· Normalize
the sum
· Round
off the result
· Check
for overflow
Figure
6.17 of the text
book.
Example
1
Perform
addition of the following
floatingpoint numbers.
0.510
, 0.437510
Binary:
0.510 = 1/210=
0.12= 1.000 x
21
0.437510= 7/1610 =
7/24= 0.01112 = 
1.110 x 22
Align:
1.110 x 22 → 0.111 x
21
Addition:
1.000 x 21 + (0.111 x 21)
= 0.001 x 21
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Advanced Computer
ArchitectureCS501
________________________________________________________
Normalization
of Sum:
0.001
2 x 21=
0.0102 x 22
= 1.000
2 x 24
Hardware
Structure for FloatingPoint
Add and Subtract
Figure
6.17 of the text
book.
FloatingPoint
Multiplication
The
floatingpoint multiplication uses
the following steps:
· Unpack
sign, exponent and
significands
· Apply
exclusiveor operation to signs,
add exponents and then
multiply
significands.
· Normalize,
round and shift the
result.
· Check
the result for
overflow.
· Pack
the result and report
exceptions.
FloatingPoint
Division
The
floatingpoint division uses
the following steps:
· Unpack
sign, exponent and
significands
· Apply
exclusiveor operation to signs,
subtract the exponents and
then divide the
significands.
· Normalize,
round and shift the
result.
· Check
the result for
overflow.
· Pack
the result and report
exceptions.
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Modified: 01Nov06
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