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Advance Computer Architecture

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Advanced Computer Architecture-CS501
Advanced Computer Architecture
Lecture No. 38
Reading Material
Vincent P. Heuring & Harry F. Jordan
Chapter 7
Computer Systems Design and Architecture
7.2.6, 7.3
Memory Modules
Read Only Memory (ROM)
Memory Module
Static RAM chips can be assembled into systems without changing the timing
characteristics of a memory access. Dynamic RAM chips, however, have enough timing
complexity that a memory module built from dynamic RAM chips will have complex
control. The cause of timing complexity is the time-multiplexed row and column
addresses, and the refresh operation.
Word Assembly from Narrow Chips
Chips can be combined to expand the memory word size while keeping the same number
of words. Address, chip select, and R/W signals are connected in parallel to all the chips.
Only the data signals are kept separate, with those from each chip supplying different bits
of the wider word. For high capacity memory chips, narrow words are used. This is
because adding a data pin to a chip with 2m words of s bits increases the number of bits it
can store by only a factor of (s+1)/s, while adding an address pin always doubles the
Dynamic RAM Module with Refresh Control
For Dynamic RAM chips the total address is divided into row and column address. Row
address strobe signal RAS and a column strobe signal CAS are used to differentiate
between these two signals.
Read Only Memory (ROM)
ROM is the read-only memory which contains permanent pattern of data that cannot be
changed. ROM is nonvolatile i.e. it retains the information in it when power is removed
from it. Different types of ROMs are discussed below.
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Advanced Computer Architecture-CS501
The PROM stands for Programmable Read only Memory. It is also nonvolatile and may
be written into only once. For PROM, the writing process is performed electrically in the
field. PROMs provide flexibility and convenience.
Erasable Programmable Read-only Memory or EPROM chips have quartz windows and
by applying ultraviolet light erase the data can be erased from the EPROM. Data can be
restored in an EPROM after erasure. EPROMs are more expensive than PROMs and are
generally used for prototyping or small-quantity, special purpose work.
EEPROM stands for Electrically Erasable Programmable Read-only Memory. This is a
read-mostly memory that can be written into at any time without erasing prior contents;
only the byte or bytes addressed are updated. The write operation takes considerably
longer than the read operation. It is more expensive than EPROM.
Flash Memory
An entire flash memory can be erased in one or a few seconds, which is much faster than
EPROM. In addition, it is possible to erase just blocks of memory rather than an entire
Cache by definition is a place for safe storage and provides the fastest possible storage
after the registers. The cache contains a copy of portions of the main memory. When the
CPU attempts to read a word from memory, a check is made to determine if the word is
in the cache. If so, the word is delivered to the CPU. If not, a block of the main memory,
consisting of some fixed number of words, is read into the cache and then the word is
delivered to the CPU.
Spatial Locality
This would mean that in a part of a program, if we have a particular address being
accessed then it is highly probable that the data available at the next address would be
highly accessed.
Temporal Correlation
In this case, we say that at a particular time, if we have utilized a particular part of the
memory then we might access the adjacent parts very soon.
Cache Hit and Miss
When the CPU needs some data, it communicates with the cache, and if the data is
available in the cache, we say that a cache hit has occured. If the data is not available in
the cache then it interacts with the main memory and fetches an appropriate block of data.
This is a cache miss.
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Table of Contents:
  1. Computer Architecture, Organization and Design
  2. Foundations of Computer Architecture, RISC and CISC
  3. Measures of Performance SRC Features and Instruction Formats
  4. ISA, Instruction Formats, Coding and Hand Assembly
  5. Reverse Assembly, SRC in the form of RTL
  6. RTL to Describe the SRC, Register Transfer using Digital Logic Circuits
  7. Thinking Process for ISA Design
  8. Introduction to the ISA of the FALCON-A and Examples
  9. Behavioral Register Transfer Language for FALCON-A, The EAGLE
  10. The FALCON-E, Instruction Set Architecture Comparison
  11. CISC microprocessor:The Motorola MC68000, RISC Architecture:The SPARC
  12. Design Process, Uni-Bus implementation for the SRC, Structural RTL for the SRC instructions
  13. Structural RTL Description of the SRC and FALCON-A
  14. External FALCON-A CPU Interface
  15. Logic Design for the Uni-bus SRC, Control Signals Generation in SRC
  16. Control Unit, 2-Bus Implementation of the SRC Data Path
  17. 3-bus implementation for the SRC, Machine Exceptions, Reset
  18. SRC Exception Processing Mechanism, Pipelining, Pipeline Design
  19. Adapting SRC instructions for Pipelined, Control Signals
  20. SRC, RTL, Data Dependence Distance, Forwarding, Compiler Solution to Hazards
  21. Data Forwarding Hardware, Superscalar, VLIW Architecture
  22. Microprogramming, General Microcoded Controller, Horizontal and Vertical Schemes
  23. I/O Subsystems, Components, Memory Mapped vs Isolated, Serial and Parallel Transfers
  24. Designing Parallel Input Output Ports, SAD, NUXI, Address Decoder , Delay Interval
  25. Designing a Parallel Input Port, Memory Mapped Input Output Ports, wrap around, Data Bus Multiplexing
  26. Programmed Input Output for FALCON-A and SRC
  27. Programmed Input Output Driver for SRC, Input Output
  28. Comparison of Interrupt driven Input Output and Polling
  29. Preparing source files for FALSIM, FALCON-A assembly language techniques
  30. Nested Interrupts, Interrupt Mask, DMA
  31. Direct Memory Access - DMA
  32. Semiconductor Memory vs Hard Disk, Mechanical Delays and Flash Memory
  33. Hard Drive Technologies
  34. Arithmetic Logic Shift Unit - ALSU, Radix Conversion, Fixed Point Numbers
  35. Overflow, Implementations of the adder, Unsigned and Signed Multiplication
  36. NxN Crossbar Design for Barrel Rotator, IEEE Floating-Point, Addition, Subtraction, Multiplication, Division
  37. CPU to Memory Interface, Static RAM, One two Dimensional Memory Cells, Matrix and Tree Decoders
  38. Memory Modules, Read Only Memory, ROM, Cache
  39. Cache Organization and Functions, Cache Controller Logic, Cache Strategies
  40. Virtual Memory Organization
  41. DRAM, Pipelining, Pre-charging and Parallelism, Hit Rate and Miss Rate, Access Time, Cache
  42. Performance of I/O Subsystems, Server Utilization, Asynchronous I/O and operating system
  43. Difference between distributed computing and computer networks
  44. Physical Media, Shared Medium, Switched Medium, Network Topologies, Seven-layer OSI Model