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Digital Logic Design

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CS302 - Digital Logic & Design
Lesson No. 36
EXAMPLE4: 3-BIT UP/DOWN COUNTER
The 3-bit Up/Down Counter was earlier implemented using J-K flip-flops. A D flip-flop
based 3-bit Up/Down Counter is implemented by mapping the present state and next state
information in D Input table. Table 36.1. The Karnaugh maps and the simplified Boolean
expressions derived from the D Input table, table 36.2 are used to implement the 3-bit
Up/Down counter circuit. Figure 36.1
Present State
Next State X=0
D flip-flop inputs
Q2
Q1
Q0
Q2
Q1
Q0
D2
D1
D0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Table 36.1a
D flip-flop input table for X=0
Present State
Next State X=1
D flip-flop inputs
Q2
Q1
Q0
Q2
Q1
Q0
D2
D1
D0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
0
1
1
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
0
1
1
0
Table 36.1b
D flip-flop input table for X=1
Q2Q1/Q0X
00
01
11
10
00
0
1
0
0
01
0
0
0
1
11
1
1
1
0
10
1
0
1
1
D  2 = Q  2 Q1 Q  0 X + Q  2Q1Q  0 X + Q  2 Q  0 X + Q  2Q1 X + Q  2 Q1Q  0
Table 36.2a
Boolean expression for D2 inputs
Q2Q1/Q0X
00
01
11
10
00
0
1
0
1
01
1
0
1
0
11
1
0
1
0
10
0
1
0
1
367
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CS302 - Digital Logic & Design
D1 = Q1 Q  0 X + Q1 Q  0 X + Q1Q  0 X + Q1Q  0 X
D1 = (Q1 Q  0 + Q1Q  0 )X + (Q1 Q  0 + Q1Q  0 )X
D1 = Q  0 Q1 X
Table 36.2b
Boolean expression for D1 inputs
Q2Q1/Q0X
00
01
11
10
00
1
1
0
0
01
1
1
0
0
11
1
1
0
0
10
1
1
0
0
D0 = Q0
Table 36.2c
Boolean expression for D0 inputs
X=0 (up)
X=1 (down)
Q1
Q2
Q0
SET
SET
SET
D
D
D
Q
Q
Q
flip-flop 2
flip-flop 1
flip-flop 3
Q
Q
Q
CLR
CLR
CLR
CLK
Clear
Figure 36.1  3-bit Up/Down Counter
The main definitions and declarations of the ABEL input file for the Up/Down Counter is
shown. Table 36.3.
Pin Definition
CLOCK, CLEAR, X
pin 1, 2, 3;
Q0, Q1, Q2
pin 21, 22, 23 ISTYPE `reg,buffer';
Table 36.3a
Input/Output Pin Definition of 3-bit Up/Down Counter
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CS302 - Digital Logic & Design
The Clock, Clear and X input variables applied at pins 1, 2 and 3 are used to provide the clock
signal, the asynchronous clear pulse and the external input to control the direction of the count
sequence. The Q0, Q1 and Q2 outputs are available from the D flip-flops of the three OLMCs
at pins 21, 22 and 23. Since these outputs are sequential outputs available from the flip-flops
therefore they are defined of type register `reg.buffer'. The three outputs are the State
variables that define the different states. Table 36.3a
Equations
Q0 := !Q0;
Q1 := Q0 $ Q1 $ X;
Q2 := !Q2 & !Q1 & !Q0 & X # !Q2 & Q1 & Q0 & !X # Q2 & !Q0 & !X
# Q2 & Q1 & X # Q2 & !Q1 & Q0;
[Q0, Q1, Q2].CLK = clock;
[Q0, Q1, Q2].AR = !clear;
Table 36.3b
Equation Definition of 3-bit Up/Down Counter
The ABEL Equations definition defines the Next state outputs for the three state variables. The
ABEL assignment equations represent the Boolean expressions derived for the three D flip-
flop inputs, table 36.2. Thus the next state output for variable Q0 depends upon the D0 input
which is defined by the Boolean expression as Q  0 . Similarly, for the next state output for
variable Q1 depends upon the D1 input which is defined by the Boolean expression
as Q  0 Q1 X . The ABEL next state expression for state variable Q3 is similarly based on the
Boolean expression for Q3.
The ABEL statements [Q0, Q1, Q2].CLK = clock and [Q0, Q1, Q2].AR = !clear declare
the change from the present state to the next state on a clock transition and the Asynchronous
reset (AR) of all the three D flip-flops in the OLMC by the Clear input signal. Table 36.3b
The Test Vector definition defines the test vectors for all the three counter inputs and
the three counter outputs. Since the Asynchronous input overrides the Synchronous X input,
therefore in the first test vector when the Clear Asynchronous input is 0 the output is cleared to
000 irrespective of the X Synchronous input. When the Clear input is set to 1, the counter
functions normally, the X input set to 0 sets the counter to increment and the X input set to 1
sets the counter to decrement. Table 36.3c
Test Vector
([Clock, Clear, X] -> [Q2, Q1, Q0])
[ .c. ,  0  ,.x.] -> [0 , 0 , 0 ];
[ .c. ,  1  , 0 ] -> [0 , 0 , 1 ];
[ .c. ,  1  , 0 ] -> [0 , 1 , 0 ];
[ .c. ,  1  , 0 ] -> [0 , 1 , 1 ];
[ .c. ,  1  , 0 ] -> [1 , 0 , 0 ];
[ .c. ,  1  , 0 ] -> [1 , 0 , 1 ];
[ .c. ,  1  , 0 ] -> [1 , 1 , 0 ];
[ .c. ,  1  , 0 ] -> [1 , 1 , 1 ];
[ .c. ,  1  , 0 ] -> [0 , 0 , 0 ];
[ .c. ,  1  , 1 ] -> [1 , 1 , 1 ];
[ .c. ,  1  , 1 ] -> [1 , 1 , 0 ];
[ .c. ,  1  , 1 ] -> [1 , 0 , 1 ];
[ .c. ,  1  , 1 ] -> [1 , 0 , 0 ];
369
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CS302 - Digital Logic & Design
[
.c.
,
1
, 1 ] -> [0
,
1
,
1 ];
[
.c.
,
1
, 1 ] -> [0
,
1
,
0 ];
[
.c.
,
1
, 1 ] -> [0
,
0
,
1 ];
[
.c.
,
1
, 1 ] -> [0
,
0
,
0 ];
Table 36.3c Test Vector Definition of 3-bit Up/Down Counter
Using a Truth-Table to specify Sequential Circuit
The ABEL Input file can use a truth table instead of the equation to specify the Boolean
expressions. The Equation definition of the ABEL input file reduces to the two statements
defining the change in the output state based on the clock transition and the Asynchronous
reset of the D flip-flops through the Asynchronous Clear signal. Table 36.4a.
Equations
[Q0, Q1, Q2].CLK = clock;
[Q0, Q1, Q2].AR = !clear;
Table 36.4a
Equation Definition for Truth Table based Sequential Circuit definition
The 3-bit Up/Down Sequential circuit's complete operation can be described by a truth table
which has external inputs Clear, X and Present State variables Q0, Q1 and Q2. The output of
the counter circuit are the Next State variables Q0, Q1, Q2. The first statement of the truth
table definition indicates that when Clear is set to 0, the counter output is reset to 000
irrespective of the X input and the present state inputs. The next 16 statements define the 8
input combinations and the corresponding counter outputs when the counter is counting up
and the 8 input combinations and its corresponding outputs when the counter is counting
down. Table 36.4b.
Truth Table
Truth_Table
([Clear, X, Q2, Q1, Q0] :> [Q2, Q1, Q0])
[ 0  ,.x., .x. , .x. , .x. ] :> [ 0 , 0 , 0 ];
[ 1  , 0 , 0 , 0 , 0 ] :> [ 0 , 0 , 1 ];
[ 1  , 0 , 0 , 0 , 1 ] :> [ 0 , 1 , 0 ];
[ 1  , 0 , 0 , 1 , 0 ] :> [ 0 , 1 , 1 ];
[ 1  , 0 , 0 , 1 , 1 ] :> [ 1 , 0 , 0 ];
[ 1  , 0 , 1 , 0 , 0 ] :> [ 1 , 0 , 1 ];
[ 1  , 0 , 1 , 0 , 1 ] :> [ 1 , 1 , 0 ];
[ 1  , 0 , 1 , 1 , 0 ] :> [ 1 , 1 , 1 ];
[ 1  , 0 , 1 , 1 , 1 ] :> [ 0 , 0 , 0 ];
[ 1  , 1 , 0 , 0 , 0 ] :> [ 1 , 1 , 1 ];
[ 1  , 1 , 1 , 1 , 1 ] :> [ 1 , 1 , 0 ];
[ 1  , 1 , 1 , 1 , 0 ] :> [ 1 , 0 , 1 ];
[ 1  , 1 , 1 , 0 , 1 ] :> [ 1 , 0 , 0 ];
[ 1  , 1 , 1 , 0 , 0 ] :> [ 0 , 1 , 1 ];
[ 1  , 1 , 0 , 1 , 1 ] :> [ 0 , 1 , 0 ];
[ 1  , 1 , 0 , 1 , 0 ] :> [ 0 , 0 , 1 ];
[ 1  , 1 , 0 , 0 , 1 ] :> [ 0 , 0 , 0 ];
Table 36.4b
Truth Table definition for the 3-bit Up/Down Counter
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CS302 - Digital Logic & Design
Using a State Diagram to specify Sequential Circuit
The ABEL Input file can also use a State diagram to specify the states of the Sequential
circuit. Before specifying the State diagram, the states have to be defined. After defining the
states the state diagram is defined by indicating how the present state changes to the next
state. ABEL, IF-THEN-ELSE statements or GOTO statements are used to specify the how the
present state changes to the next state.
State Definition
QSTATE
= [Q2, Q1, Q0];
A
= [ 0 , 0 , 0 ];
B
= [ 0 , 0 , 1 ];
C
= [ 0 , 1 , 0 ];
D
= [ 0 , 1 , 1 ];
E
= [ 1 , 0 , 0 ];
F
= [ 1 , 0 , 1 ];
G
= [ 1 , 1 , 0 ];
H
= [ 1 , 1 , 1 ];
Table 36.5a
State definition of the 3-bit Up/Down Counter
The QSTATE variable defines the eight states of the counter circuit. Each state defined by the
three state variables is identified by state names A, B to H. Table 36.5a.
State Diagram
State A:
if X then H else B;
State B:
if X then A else C;
State C:
if X then B else D;
State D:
if X then C else E;
State E:
if X then D else F;
State F:
if X then E else G;
State G:
if X then F else H;
State H:
if X then G else A;
Table 36.5b
Defining the next states using IF-THEN-ELSE
The ABEL, IF-THEN-ELSE statements are used to define the input conditions for which the
present state changes to the next state. For example, in the State Diagram, the State A
changes to state H if the input variable X=1 otherwise the next state is state B. Similar, if then
else statements are used to define the next states for each of the present states. If the present
state switches to the next state without checking any conditions then an ABEL, GOTO
statement is used. For example, for a 3-bit Up counter GOTO statements are used to specify
the next state without checking any condition. Table 36.5c
State Diagram
State A:
GOTO B;
State B:
GOTO C;
State C:
GOTO D;
State D:
GOTO E;
State E:
GOTO F;
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CS302 - Digital Logic & Design
State F:
GOTO G;
State G:
GOTO H;
State H:
GOTO A;
Table 36.5c
Defining the next states using GOTO
The ABEL Input file which uses the State diagram instead of equations or the truth table
replaces the Equation part by State Definitions and State Diagram. The Equation definition
only defines the change in state on a clock transition and the Asynchronous input as shown in
table 36.4a
Design Example: Elevator Control System
An elevator is installed in a building that moves from one floor to the other. A person
going to the second floor from the first floor presses a request button on the first floor. When
the elevator arrives at the first floor, the doors open and the person walks in to the elevator.
The person presses the request button for the second floor. When the elevator reaches the
second floor, it stops and the doors open. The doors are opened for a specified time. A person
inside the elevator can keep the doors open for a longer duration of time if an `Open' button is
pressed. Inside the elevator and outside near each entrance to the elevator there is a 7-
segment display which displays the floor on which the elevator currently is. The direction, Up
or Down in which the elevator is moving is also displayed.
Input and Output Signals
Different inputs and outputs are required to control the operation of the elevator. The
operation of the elevator is based on a sequential state machine. A State diagram describes
all the operations of the elevator. The inputs that are received from the person in the form of
requests are
·
Request buttons to call the elevator, REQ1 and REQ2
·
Floor request buttons inside the elevator, FLOOR1 and FLOOR2
·
Open door button, OPEN
The duration for which the elevator doors are opened, and remain open, and the time it takes
for the elevator to move form one floor to the next is determined by a clock signal. When the
elevator arrives at a floor a floor sensor generates an ARRIVE signal. Thus the State machine
uses to additional input signals.
·
Clock signal, CLOCK
·
Arrive signal, ARRIVE
The elevator generates three output signals to indicate the doors OPEN/CLOSED, direction of
movement of elevator UP/DOWN and the motion of the elevator WAITING/MOVING.
·
Door Open/Close, DOOR=0 and DOOR=1
·
Direction Up/Down, DIR=0 and DIR=1
·
Motion Waiting /Moving, MOTION=0 and MOTION=1
In addition to the three output signals the elevator generates signals to display the floor
number and the direction in which the elevator is moving.
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CS302 - Digital Logic & Design
Elevator State Diagram
The State diagram of the elevator operation has six states. Figure 36.2. Three state variables
are required to define the six states. The state outputs directly determine the status of the
door, the direction of the motion and control the motion.
REQ2.FLOOR2
ARRIVE
REQ1 + OPEN
REQ2 + FLOOR2
REQ1 + FLOOR1
REQ2 + FLOOR2
REQ1 + FLOOR1
REQ2 + OPEN
ARRIVE
REQ1.FLOOR1
Figure 36.2
State Diagram of Elevator
Wait 1 State (W1): The initial state of the elevator is the Wait 1 State (W1), where the elevator
is waiting on the first floor with the door open. The W1 state 000 identifies the state outputs.
·  Door=0
(open)
·  Motion=0 (waiting)
·  Dir=0
(up)
Close 1 State (C1): If for a fixed interval of time, a request from second floor is not received or
the button for floor 2 is not pressed, the system goes to state Close1 (C1). In this state the
elevator remains on the first floor with its doors closed. The C1 state 100 identifies the output
signals.
·  Door=1
(close)
·  Motion=0 (waiting)
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CS302 - Digital Logic & Design
·
Dir=0
(up)
If at any time a person inside the elevator presses the Open door switch, OPEN or a
person waiting on first floor requests for the elevator REQ1, the system switches back to Wait
1 State, W1.
Up State (U): The system switches to Up state (U) when either a request is received from the
second floor REQ2 or a person presses the Floor2 switch F2. The U State represents the state
when the elevator is moving up. The outputs of this state are 110.
·  Door=1
(close)
·  Motion=1 (moving)
·  Dir=0
(up)
Similarly when the system is in state W1, the system switches to Up state (U), when either a
request is received from the second floor REQ2 or a person presses the Floor2 switch F2.
Wait 2 State (W2): The system switches from Up state (U), to Wait 2 state (W2) when the
Arrive signal is received from the floor sensor. In the W2 state the elevator is waiting on floor 2
with its door open. The output of the W2 state are 001
·  Door=0
(open)
·  Motion=0 (waiting)
·  Dir=1
(down)
Close 2 State (C2): The elevator waits with its door open on the second floor for a specified
period of time. If a request from first floor is not received or the button for floor 1 is not
pressed, the system switches to Close2 state (C2). In this state the elevator remains on the
second floor with its doors close. The output signals of C2 state are 101
·  Door=1
(close)
·  Motion=0 (waiting)
·  Dir=1
(down)
If at any time a person inside the elevator presses the Open door switch, OPEN or a
person waiting on second floor requests for the elevator REQ2, the system switches back to
Wait 2 State, W2.
Down State (D): The system switches to Down state (D), when either a request is received
from the first floor REQ1 or a person presses the Floor1 switch F1. The D, Down represents
the state when the elevator is moving down. The outputs of this state are 111.
·  Door=1
(close)
·  Motion=1 (moving)
·  Dir=1
(down)
Similarly when the system is in state W2, the system switches to state D, Down when either a
request is received from the first floor REQ1 or a person presses the Floor1 switch F1.The
system switches to the Wait 1 state (W1) when the Arrive signal is received from the floor
sensor on the first floor.
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CS302 - Digital Logic & Design
State Table
Present
Next
Next
Next State
Next State
Next
Next
State
State
State
State
State
REQ1=0
REQ1=1
FLOOR1=0
FLOOR1=1
OPEN=0
OPEN=1
W1(000) x
x
x
x
x
x
C1(100)  C1
W1
x
x
C1
W1
UP(110)  x
x
x
x
x
x
W2(001) C2
DO
C2
DO
x
x
C2(101)  C2
DO
C2
DO
x
x
DO(111) x
x
x
x
x
x
Table 36.6a
State table for Elevator Control for REQ1, FLOOR1 and OPEN inputs
Present
Next
Next
Next State
Next State
Next
Next
State
State
State
State
State
REQ2=0
REQ2=1
FLOOR2=0
FLOOR2=1
OPEN=0
OPEN=1
W1(000) C1
UP
C1
UP
x
x
C1(100)  C1
UP
C1
UP
x
x
UP(110)  x
x
x
x
x
x
W2(001) x
x
x
x
x
x
C2(101)  C2
W2
x
x
C2
W2
DO(111) x
x
x
x
x
x
Table 36.6b
State table for Elevator Control for REQ2, FLOOR2 and OPEN inputs
The Next State tables for the Elevator Control are obtained directly from the State Diagram.
The State table show the present and the next states for each of the five external inputs that
are activated by people using the elevator. The ARRIVE external input is activated by a
separate sensor circuit and is not activated by press of a button. The next states when the
ARRIVE signal is active are not shown in the State Tables.
Input Latches
The request buttons to call the elevator, REQ1 and REQ2, the Floor request buttons
inside the elevator, F1 and F2 and the Open door button, OPEN can be pressed at any time. A
sequential circuit switches from one state to the next on the basis of its present state and
external input. Supposedly, a person presses and releases the REQ1 button to request for the
elevator in a time period between two consecutive clock transitions. At the clock transition, the
status of the REQ1 switch is inactive therefore the REQ1 is not entertained. It is therefore
important that all input buttons, REQ1, REQ2, F1, F2 and OPEN are connected through
latches which are not controlled by a clock signal. Figure 36.3. A total of 5 latches are required
to store the inputs received from the buttons REQ1, REQ2, F1, F2 and OPEN.
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CS302 - Digital Logic & Design
Figure 36.3 Block diagram of the Elevator State Machine
376
Table of Contents:
  1. AN OVERVIEW & NUMBER SYSTEMS
  2. Binary to Decimal to Binary conversion, Binary Arithmetic, 1’s & 2’s complement
  3. Range of Numbers and Overflow, Floating-Point, Hexadecimal Numbers
  4. Octal Numbers, Octal to Binary Decimal to Octal Conversion
  5. LOGIC GATES: AND Gate, OR Gate, NOT Gate, NAND Gate
  6. AND OR NAND XOR XNOR Gate Implementation and Applications
  7. DC Supply Voltage, TTL Logic Levels, Noise Margin, Power Dissipation
  8. Boolean Addition, Multiplication, Commutative Law, Associative Law, Distributive Law, Demorgan’s Theorems
  9. Simplification of Boolean Expression, Standard POS form, Minterms and Maxterms
  10. KARNAUGH MAP, Mapping a non-standard SOP Expression
  11. Converting between POS and SOP using the K-map
  12. COMPARATOR: Quine-McCluskey Simplification Method
  13. ODD-PRIME NUMBER DETECTOR, Combinational Circuit Implementation
  14. IMPLEMENTATION OF AN ODD-PARITY GENERATOR CIRCUIT
  15. BCD ADDER: 2-digit BCD Adder, A 4-bit Adder Subtracter Unit
  16. 16-BIT ALU, MSI 4-bit Comparator, Decoders
  17. BCD to 7-Segment Decoder, Decimal-to-BCD Encoder
  18. 2-INPUT 4-BIT MULTIPLEXER, 8, 16-Input Multiplexer, Logic Function Generator
  19. Applications of Demultiplexer, PROM, PLA, PAL, GAL
  20. OLMC Combinational Mode, Tri-State Buffers, The GAL16V8, Introduction to ABEL
  21. OLMC for GAL16V8, Tri-state Buffer and OLMC output pin
  22. Implementation of Quad MUX, Latches and Flip-Flops
  23. APPLICATION OF S-R LATCH, Edge-Triggered D Flip-Flop, J-K Flip-flop
  24. Data Storage using D-flip-flop, Synchronizing Asynchronous inputs using D flip-flop
  25. Dual Positive-Edge triggered D flip-flop, J-K flip-flop, Master-Slave Flip-Flops
  26. THE 555 TIMER: Race Conditions, Asynchronous, Ripple Counters
  27. Down Counter with truncated sequence, 4-bit Synchronous Decade Counter
  28. Mod-n Synchronous Counter, Cascading Counters, Up-Down Counter
  29. Integrated Circuit Up Down Decade Counter Design and Applications
  30. DIGITAL CLOCK: Clocked Synchronous State Machines
  31. NEXT-STATE TABLE: Flip-flop Transition Table, Karnaugh Maps
  32. D FLIP-FLOP BASED IMPLEMENTATION
  33. Moore Machine State Diagram, Mealy Machine State Diagram, Karnaugh Maps
  34. SHIFT REGISTERS: Serial In/Shift Left,Right/Serial Out Operation
  35. APPLICATIONS OF SHIFT REGISTERS: Serial-to-Parallel Converter
  36. Elevator Control System: Elevator State Diagram, State Table, Input and Output Signals, Input Latches
  37. Traffic Signal Control System: Switching of Traffic Lights, Inputs and Outputs, State Machine
  38. Traffic Signal Control System: EQUATION DEFINITION
  39. Memory Organization, Capacity, Density, Signals and Basic Operations, Read, Write, Address, data Signals
  40. Memory Read, Write Cycle, Synchronous Burst SRAM, Dynamic RAM
  41. Burst, Distributed Refresh, Types of DRAMs, ROM Read-Only Memory, Mask ROM
  42. First In-First Out (FIFO) Memory
  43. LAST IN-FIRST OUT (LIFO) MEMORY
  44. THE LOGIC BLOCK: Analogue to Digital Conversion, Logic Element, Look-Up Table
  45. SUCCESSIVE –APPROXIMATION ANALOGUE TO DIGITAL CONVERTER