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Digital Logic Design

AN OVERVIEW & NUMBER SYSTEMS
Binary to Decimal to Binary conversion, Binary Arithmetic, 1’s & 2’s complement
Range of Numbers and Overflow, Floating-Point, Hexadecimal Numbers
Octal Numbers, Octal to Binary Decimal to Octal Conversion
LOGIC GATES: AND Gate, OR Gate, NOT Gate, NAND Gate
AND OR NAND XOR XNOR Gate Implementation and Applications
DC Supply Voltage, TTL Logic Levels, Noise Margin, Power Dissipation
Boolean Addition, Multiplication, Commutative Law, Associative Law, Distributive Law, Demorgan’s Theorems
Simplification of Boolean Expression, Standard POS form, Minterms and Maxterms
KARNAUGH MAP, Mapping a non-standard SOP Expression
Converting between POS and SOP using the K-map
COMPARATOR: Quine-McCluskey Simplification Method
ODD-PRIME NUMBER DETECTOR, Combinational Circuit Implementation
IMPLEMENTATION OF AN ODD-PARITY GENERATOR CIRCUIT
BCD ADDER: 2-digit BCD Adder, A 4-bit Adder Subtracter Unit
16-BIT ALU, MSI 4-bit Comparator, Decoders
BCD to 7-Segment Decoder, Decimal-to-BCD Encoder
2-INPUT 4-BIT MULTIPLEXER, 8, 16-Input Multiplexer, Logic Function Generator
Applications of Demultiplexer, PROM, PLA, PAL, GAL
OLMC Combinational Mode, Tri-State Buffers, The GAL16V8, Introduction to ABEL
OLMC for GAL16V8, Tri-state Buffer and OLMC output pin
Implementation of Quad MUX, Latches and Flip-Flops
APPLICATION OF S-R LATCH, Edge-Triggered D Flip-Flop, J-K Flip-flop
Data Storage using D-flip-flop, Synchronizing Asynchronous inputs using D flip-flop
Dual Positive-Edge triggered D flip-flop, J-K flip-flop, Master-Slave Flip-Flops
THE 555 TIMER: Race Conditions, Asynchronous, Ripple Counters
Down Counter with truncated sequence, 4-bit Synchronous Decade Counter
Mod-n Synchronous Counter, Cascading Counters, Up-Down Counter
Integrated Circuit Up Down Decade Counter Design and Applications
DIGITAL CLOCK: Clocked Synchronous State Machines
NEXT-STATE TABLE: Flip-flop Transition Table, Karnaugh Maps
D FLIP-FLOP BASED IMPLEMENTATION
Moore Machine State Diagram, Mealy Machine State Diagram, Karnaugh Maps
SHIFT REGISTERS: Serial In/Shift Left,Right/Serial Out Operation
APPLICATIONS OF SHIFT REGISTERS: Serial-to-Parallel Converter
Elevator Control System: Elevator State Diagram, State Table, Input and Output Signals, Input Latches
Traffic Signal Control System: Switching of Traffic Lights, Inputs and Outputs, State Machine
Traffic Signal Control System: EQUATION DEFINITION
Memory Organization, Capacity, Density, Signals and Basic Operations, Read, Write, Address, data Signals
Memory Read, Write Cycle, Synchronous Burst SRAM, Dynamic RAM
Burst, Distributed Refresh, Types of DRAMs, ROM Read-Only Memory, Mask ROM
First In-First Out (FIFO) Memory
LAST IN-FIRST OUT (LIFO) MEMORY
THE LOGIC BLOCK: Analogue to Digital Conversion, Logic Element, Look-Up Table
SUCCESSIVE –APPROXIMATION ANALOGUE TO DIGITAL CONVERTER

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