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Computer Science
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Digital Logic Design |
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AN OVERVIEW & NUMBER SYSTEMS
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Binary to Decimal to Binary conversion, Binary Arithmetic, 1’s & 2’s complement
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Range of Numbers and Overflow, Floating-Point, Hexadecimal Numbers
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Octal Numbers, Octal to Binary Decimal to Octal Conversion
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LOGIC GATES: AND Gate, OR Gate, NOT Gate, NAND Gate
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AND OR NAND XOR XNOR Gate Implementation and Applications
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DC Supply Voltage, TTL Logic Levels, Noise Margin, Power Dissipation
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Boolean Addition, Multiplication, Commutative Law, Associative Law, Distributive Law, Demorgan’s Theorems
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Simplification of Boolean Expression, Standard POS form, Minterms and Maxterms
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KARNAUGH MAP, Mapping a non-standard SOP Expression
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Converting between POS and SOP using the K-map
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COMPARATOR: Quine-McCluskey Simplification Method
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ODD-PRIME NUMBER DETECTOR, Combinational Circuit Implementation
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IMPLEMENTATION OF AN ODD-PARITY GENERATOR CIRCUIT
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BCD ADDER: 2-digit BCD Adder, A 4-bit Adder Subtracter Unit
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16-BIT ALU, MSI 4-bit Comparator, Decoders
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BCD to 7-Segment Decoder, Decimal-to-BCD Encoder
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2-INPUT 4-BIT MULTIPLEXER, 8, 16-Input Multiplexer, Logic Function Generator
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Applications of Demultiplexer, PROM, PLA, PAL, GAL
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OLMC Combinational Mode, Tri-State Buffers, The GAL16V8, Introduction to ABEL
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OLMC for GAL16V8, Tri-state Buffer and OLMC output pin
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Implementation of Quad MUX, Latches and Flip-Flops
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APPLICATION OF S-R LATCH, Edge-Triggered D Flip-Flop, J-K Flip-flop
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Data Storage using D-flip-flop, Synchronizing Asynchronous inputs using D flip-flop
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Dual Positive-Edge triggered D flip-flop, J-K flip-flop, Master-Slave Flip-Flops
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THE 555 TIMER: Race Conditions, Asynchronous, Ripple Counters
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Down Counter with truncated sequence, 4-bit Synchronous Decade Counter
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Mod-n Synchronous Counter, Cascading Counters, Up-Down Counter
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Integrated Circuit Up Down Decade Counter Design and Applications
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DIGITAL CLOCK: Clocked Synchronous State Machines
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NEXT-STATE TABLE: Flip-flop Transition Table, Karnaugh Maps
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D FLIP-FLOP BASED IMPLEMENTATION
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Moore Machine State Diagram, Mealy Machine State Diagram, Karnaugh Maps
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SHIFT REGISTERS: Serial In/Shift Left,Right/Serial Out Operation
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APPLICATIONS OF SHIFT REGISTERS: Serial-to-Parallel Converter
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Elevator Control System: Elevator State Diagram, State Table, Input and Output Signals, Input Latches
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Traffic Signal Control System: Switching of Traffic Lights, Inputs and Outputs, State Machine
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Traffic Signal Control System: EQUATION DEFINITION
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Memory Organization, Capacity, Density, Signals and Basic Operations, Read, Write, Address, data Signals
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Memory Read, Write Cycle, Synchronous Burst SRAM, Dynamic RAM
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Burst, Distributed Refresh, Types of DRAMs, ROM Read-Only Memory, Mask ROM
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First In-First Out (FIFO) Memory
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LAST IN-FIRST OUT (LIFO) MEMORY
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THE LOGIC BLOCK: Analogue to Digital Conversion, Logic Element, Look-Up Table
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SUCCESSIVE –APPROXIMATION ANALOGUE TO DIGITAL CONVERTER
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Related Documents:
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